In electronics, “differential communication channel” refers to transmission of data by means of two signals, which have opposite polarity, that are sent simultaneously on two separate conductors, or by means of one signal, at a time, in the same polarity, where the sign of the resulting difference between the signals existing on the two conductors is interpreted as digital value “1” or “0”. Data that is sent via a differential communication channel is generally referred to as “differential digital data”, and communication of differential digital data is generally referred to as “differential communication”. In electronics, the term “crosstalk” refers to any phenomenon by which a signal transmitted on one circuit, channel, or wire, of a transmission system creates an undesired signal in another circuit, channel, or wire, due to undesired capacitive, inductive, or conductive coupling between them. The undesired signal is called “noise”, “interference”, or “disturbance.” In general, the closer the circuits, channels, or wires, the more they are prone to picking up crosstalk interference.
Common Mode Interference (“CMI”), which is a type of crosstalk interference, results from similar currents flowing in the same direction in nearby wires. This kind of electric interference is hard to isolate and to mitigate by using off-the-shelf communication interfaces. In addition, efforts traditionally have been made to cope with the implications of CMI interference in the receiver rather than coping with the CMI interference in the transmitting device. CMI is referred to in certification tests known in the art as Electromagnetic Interference (“EMI”) Tests. Differential Mode Interference (“DMI”), which is another type of crosstalk interference, results from incoherent electromagnetic field currents flowing in opposite directions in nearby conductive wires. This kind of electric interference can be mitigated by using twisted pair methodology. Common mode radiation and differential mode radiation are described in more detail in, for example, “High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices” (chapter 10.2, “Physical Mechanisms of Radiation”), by STEPHEN H. HALL et al. Professional computer network cabling must pass TIA/EIA (Telecommunications Industry Association/Electronic Industries Association) standards tests, generally TIA/EIA-568-B standard, to show that the tested computer network cabling is compliant with the corresponding communication standards, protocols, etc., for which it is intended.
The Universal Bus (“USB”) standard is widely used in computer peripherals, for example, for exchanging digital data. In general, high speed USB communication involves exchanging high speed (480 Mbits/Sec.) differential digital data via two electrical conductors. CMI and DMI are known to be an important cause of problems in differential communication such as USB communication, as they result in significant distortion in communicated signals.
FIG. 1 (prior art) schematically illustrates a typical differential communication link between one device, referred to as host device 20, and another device, referred to as device 22. The differential communication link is “” in the sense that digital data is communicated through it one binary digit at a time. Practically, host device 20 can both transmit and receive data to/from device 22. However, for the sake of simplicity, device 22 is shown having only a transmitter interface, and host device 20 is shown having only a receiver interface. Host device 20 may be, for example, a USB device that uses data sent to it from device 22, or a USB hub that functionally connects device 22 to other devices or routers, whether they have USB capability or not.
The differential communication link linking between host device 20 and device 22 includes a first conductor (“D+”, shown at 24) and a second conductor (“D−”, shown at 26), via which conductors the electric current I of current source 32 flows (but, ideally, not in both conductors simultaneously) to host device 20. A stream of binary digits “1” and “0”, which constitute digital data that is conveyed from device 22 to host device 20 via conductors 24 and 26, is generated by causing the current I to flow alternately through the D+ conductor 24 and the D− conductor 26. Specifically, one of the conductors 24, 26 is assigned for transmission of binary value “1” and the other of the conductors 24, 26 is assigned for transmission of binary value “0.” Selecting a specific conductor for a specific binary digit depends on the communication protocol or standard used. Transmission of binary value “1” is executed by directing the electric current I to the conductor selected for binary values “1”, and transmission of binary value “0” is executed by directing the electric current I to the conductor selected for binary values “0”. Whenever the binary digit that is to be transmitted changes (i.e., from “1” to “0”, or from “0” to “1”), the electric current I is diverted from one conductor to the other by using switching system 102. Thus, during data communication, binary digits are transmitted via the differential communication interface one digit at a time, such that “0s” are always transmitted using one of the conductors (e.g., conductor 24) and “0s” are always transmitted using the other conductor (e.g., conductor 26).
Switching system 102 includes controllable switches 34 and 40, and logic inverter 39. Controllable switches 34 and 40 are driven by control signals 36 and 38 that are issued by a controller (not shown in FIG. 1). Control signals 36 and 38 switch controllable switches 34 and 40, respectively, between an “open” state and a “closed” state so as to redirect, or divert, the electric current I from one conductor (e.g., from conductor 24) to another (i.e., conductor 26). Redirecting the electric current I is performed by simultaneously closing one of the switches 34 and 40 and opening the other switch. Switch 34 is switched between the closed and open states by using control signal 36, and switch 40 is switched between the closed and open states by using control signal 38, which is the logical inverse of control signal 36. Logical inversion of control signal 36 is performed by an inverter 39, which is a “break-before-make” switching device.
A logic state “1” (also known as USB logical state “K”) is generated (i.e., a binary digit “1” is transmitted from device 22 to host device 20) by simultaneously closing switch 34 (a ‘first’ switch) and opening switch 40 (a ‘second’ switch) to enable the current I to flow through switch 34, to thereby generate, on the D+termination resistors 30 and 42, a voltage that is sensed and interpreted by host device 20 as a logical state equivalently known as “D+”, “K”, or “1”. Likewise, a logic state “0” (also known as USB logical state “J”) is generated by simultaneously opening switch 34 and closing switch 40 to enable the current I to flow through switch 40, to thereby generate on the D− termination resistors 28 and 44 a voltage that is sensed and interpreted by host 20 as a logical state equivalently known as “D−”, “J”, or “0”.
An ideal switching element would generate an ideal square-like wave, which would require changing the signal from the high to the low state instantaneously and without distortions. However, practically, this is impossible to achieve because an instantaneous change would require an infinite frequency bandwidth. Regarding FIG. 1, switching between switches 34 and 40 would ideally result in the current I flowing either through switch 34, in which case I1=I and I2=0, or through switch 40, in which case I1=0 and I2=I. However, practical switches, such as switches 34 and 40, which typically are Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switches, introduce a finite transition switching time (in the range of tenths to hundreds of picoseconds (psec)) in each switching cycle. During the switching transition time both switches are in a mid-position state, meaning that each of switches 34 and 40 is neither fully closed nor fully open. This results in a portion of the current I flowing through switch 34, meaning that 0<I1<I, and another portion of the current I flowing through switch 40, meaning that 0<I2<I, where, according to Kirchhoff's Current Law (also known as “Kirchhoff's first law”), I1+I2=I at any given time. Within each transition time each of the signals C1(t) and C2(t), which respectively result from, or correspond to, the current I1 and I2, has a transition edge (not shown in FIG. 1) that has a finite slew rate. In electronics, “slew rate” represents rate of change of a signal in volts per second. Limitations in slew rate capability usually give rise to nonlinear effects in electronic amplifiers.
Choosing a slew rate is a matter of tradeoff between CMI and DMI. That is, using a fast (high) slew rate (i.e., using short transition time) results in low CMI interference, which is desirable. However, using a slew rate which is too fast results in high harmonics, which is a major cause for DMI interference. In terms of reducing DMI interference, it is, therefore, desired to use slow slew rates (that is, to use long transition times), and in terms of reducing CMI interference it is, therefore, desired to use fast slew rates (that is, to use short transition times). However, in order not to exceed allowed levels of CM and DMI interferences, communication standards limit the minimum and maximum temporal width (duration) of the transition time, which is the time period during which currents, which flow through switching elements such as switches 34 and 40, change from their minimal value to their maximal value. For example, in USB communications the maximum time period during which a current, which flows through a switching element increases from 20% to 80% (or decreases from 80% to 20%) of its maximum magnitude should not exceed approximately 500 picoseconds. Nevertheless, using even the fastest slew rate (i.e., shortest transition time) allowed by the relevant communication standards still results in some of the current I flowing both in conductor 24 and conductor 26 in the same direction, which, as explained above, is a major cause for CMI interference.
FIG. 2 shows three timing diagrams, generally shown at 201, 202, and 203, that are associated with switching system 102 of FIG. 1. Timing diagram 201 corresponds to the signal C1(t), which results from, or corresponds to, the current I1 flowing through conductor 24 (a first conductor of the involved differential communication link) and resistor R3 whenever switch 34 transitions from the open state to the closed state and controllable switch 40 transitions from the closed state to the open state. Likewise, timing diagram 202 corresponds to the signal C2(t), which results from, or corresponds to, the current I2 flowing through conductor 26 (a second conductor of the differential communication link) and resistor R4 whenever switch 40 transitions from the open state to the closed state and switch 34 transitions from the closed state to the open state.
It is noted that each of signals C1(t) and C2(t) of FIGS. 1 and 2 may be a current signal (i.e., the current signal flowing in/through the respective conductors 24 and 26), or a voltage signal that results from, correspond to, or associated with, the current signal flowing through the respective resistors 42 and 44. The waveforms of signals C1(t) and C2(t) therefore have the same, or substantially the same, shape, including the transition edges, regardless of whether C1(t) and C2(t) are current signals or voltage signals. In addition, signals C1(t) and C2(t) are shown in FIG. 2, and also in the other relevant drawings, normalized. This clarification (i.e., C(i) being current signal or voltage signal, and C(i) being normalized) is applicable to C(1) and C(2) throughout the description. In addition, the terms “C(1)” and “first signal” are interchangeable used herein, as are the terms “C(2) and “second signal”.
F(t), shown at 203, was calculated using signals C1(t) and C2(t) in the way described below. “F(t)” represents, or is indicative of, a common mode noise signal. During periods 212, switch 34 is fully closed and switch 40 is fully open, whereas during period 213 switch 34 is fully open and switch 40 is fully closed. However, as stated above, during transition times, such as during exemplary transition times 220, 221, and 222, switches 34 and 40 are in a mid-position state. Namely, during period 220, switch 34 is not yet fully open and switch 40 is not yet fully closed; during period 221, switch 34 is not yet fully closed and switch 40 is not yet fully open; and during period 222, switch 34 is not yet fully open and switch 40 is not yet fully closed.
Switches such as switches 34 and 40 of FIG. 1 are typically implemented by a MOSFET transistor. The mid-position state of an analog MOSFET switch is determined by its current-voltage (V/I) relationship. Thus, due to the current-voltage (V/I) relationship in MOSFET transistors, which is expressed in equation (1), the transition portions, or transition edges, of C1(t) and C2(t), respectively shown in 201 and 202 in FIG. 2, resemble an exponential curve. The current-voltage relationship in a MOSFET transistor is described, for example, in “CMOS, Circuit Design, Layout, and Simulation” (by R. Jacob Baker, 2nd edition, p. 142).
                                                                        I                D                            =                                                μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                                  (                                                                                    (                                                                              V                            GS                                                    -                                                      V                            th                                                                          )                                            ⁢                                              V                        DS                                                              -                                                                  V                        DS                        2                                            2                                                        )                                                                                                        =                              β                ⁢                                                                  ⁢                                  x                  [                                                                                    (                                                                              V                            GS                                                    -                                                      V                            th                                                                          )                                            ⁢                                              V                        DS                                                              -                                                                  V                        DS                        2                                            2                                                        ]                                                                                                        =                                                -                                      aV                    DS                    2                                                  +                                  bV                  DS                                                                                        (        1        )            
In equation (1), ‘ID’ is the current passing from the drain (“D”) of the MOSFET transistor to its source (“S”), ‘μn’ is the charge-carrier mobility, ‘Cox’ is the transistor's gate oxide capacitance per unit area, ‘W’ is the transistor's gate width, ‘L’ is the transistor's gate length, ‘VGS’ is the voltage between the transistor's gate (“G”) and source, ‘Vth’ is the transistor's threshold voltage, and ‘VDS’ is the voltage between the transistor's drain and source.
The instant inventor has found that the exponential-like behavior of analog MOSFET switches during transition times is a major cause of CMI interferences. The inventor has also found that the effect of this behavior on the CMI can be quantified by equation (2),F(t)=ABS{ABS[C1(t)−C2(t)]−[C1(t)+C2(t)]}  (2)where F(t) is a value calculated at time t, where ‘t’ is a point in time occurring within the transition time period(s) (220, 221 and 222), that is, during the mid-position state of the involved switches, and C1(t) and C2(t) are the signals passing through conductors 24 and 26, respectively, of FIG. 1. Outside the transition times C1(t) and C2(t) resume their normalized values of 1.0 or 0.0 and F(t) becomes 0.0.
By way of demonstration, three values of F(t), shown in 203, will now be calculated, at times t1, t2, and t3. At time t1 C1(t1)=1.0 and C2(t1)=0.0. Therefore, F(t)=ABS{ABS[1.0−0.0]−[1.0+0.0]}=0.0, shown at 231. At time t2, C1(C2)0.5 and C2(t2)=0.5. Therefore, F(t)=ABS{ABS[0.5−0.5]−[0.5+0.5]}1=0.0, shown at 232. At time t3, C1(t3)−1.0 and C2(t3)=0.0. Therefore, F(t)=ABS{ABS[0.0−1.0]−[0.0+1.0]}=0.0, shown at 233. As shown in FIG. 2, F(t) increases from 0.0 to 1.0 between t1 and t2, and decreases from 1.0 to 0.0 between t2 and t3.
Because F(t) reflects the transition characteristics of the switches, the extent to which the switches' transition times affect the CMI interference can be estimated by calculating the area under the curve of (i.e., the “energy” of) F(t) by integrating F(t) over one transition time (i.e., assuming that all, or most of the transition times are identical). In general, the greater the “energy” of F(t), the larger the detrimental effect of the switches' transitions is on the CMI interference, for which reason F(t) is also referred to herein as “common mode noise indicator” (CMNI).